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SyncMOS
F29C51002T/F29C51002B 2 MEGABIT (262,144 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
Description
TheF29C51002T/F29C51002B is a high speed 262,144 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. The F29C51002T/F29C51002B offers a combination of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O7 or by the Toggle Bit I/O6. The F29C51002T/F29C51002B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (F29C51002T) or the bottom (F29C51002B). All inputs and outputs are CMOS and TTL compatible. The F29C51002T/F29C51002B is ideal for applications that require updatable code and data storage.
Features
s s s s s s 256Kx8-bit Organization Address Access Time: 70, 90, 120, 150 ns Single 5V 10% Power Supply Sector Erase Mode Operation 16KB Boot Block (lockable) 512 bytes per Sector, 512 Sectors - Sector-Erase Cycle Time: 10ms (Max) - Byte-Write Cycle Time: 35ms (Max) Minimum 10,000 Erase-Program Cycles Low power dissipation - Active Read Current: 20mA (Typ) - Active Program Current: 30mA (Typ) - Standby Current: 100mA (Max) Hardware Data Protection Low VCC Program Inhibit Below 3.5V Self-timed write/erase operations with end-of-cycle detection - DATA Polling - Toggle Bit CMOS and TTL Interface Available in one versions - F29C51002T (Top Boot Block)
s s
s s s
s s
s Packages: - 32-pin Plastic DIP - 32-pin TSOP-I - 32-pin PLCC
Device Usage Chart
Operating Temperature Range 0C to 70 C -40C to +85C Package Outline P * * T * * J * * 70 * * Access Time (ns) 90 * * 120 * * 150 * * Power
Std.
* *
Temperature Mark Blank I
F29C51002T/F29C51002B V1.0 February 1998
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www..com
SyncMOS
F 29 C 51 002 T -
F29C51002T/F29C51002B
OPERATING VOLTAGE 51: 5V 31: 3V
DEVICE 70: 70ns 90: 90ns 12: 120ns 15: 150ns
SPEED P = PDIP T = TSOP-I J = PLCC
PKG. POWER TEMP. BLANK (0C TO 70C) I (-40C TO +85C) BLANK (STANDARD)
51002-01
BOOT BLOCK LOCATION T: TOP B: BOTTOM
Pin Configurations
VCC WE A12 A15 A16 NC
N/C A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 32-Pin PDIP 26 Top View 25 24 23 22 21 20 19 18 17
51002-02
Pin Names
A17
VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
A0-A17 I/O0-I/O7
Address Inputs Data Input/Output Chip Enable Output Enable Write Enable 5V 10% Power Supply Ground No Connect
4
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A14 A13 A8 A9 A11 OE A10 CE I/O7
CE OE WE VCC GND NC
32 Pin PLCC Top View
I/O1
I/O2
I/O3
I/O4
I/O5
GND
I/O6
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
51002-03
A11 A9 A8 A13 A14 A17 WE VCC N/C A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP I Standard Pinout Top View
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
51002-04
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Functional Block Diagram
F29C51002T/F29C51002B
X-Decoder
2,097,152 Bit Memory Cell Array
A0-A17
Address buffer & latches
Y-Decoder
CE OE WE
Control Logic
I/O Buffer & Data Latches
I/O0-I/O7
51002-07
Capacitance (1,2)
Symbol
CIN COUT CIN2
Parameter
Input Capacitance Output Capacitance Control Pin Capacitance
Test Setup
VIN = 0 VOUT = 0 VIN = 0
Typ.
6 8 8
Max.
8 12 10
Units
pF pF pF
NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25C, VCC = 5V 10%, f = 1 MHz.
Latch Up Characteristics(1)
Parameter
Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time.
Min.
-1 -1 -100
Max.
+13 VCC + 1 +100
Unit
V V mA
AC Test Load
+5.0 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 k1/2 IN3064 or Equivalent IN3064 or Equivalent
51002-08
2.7 k1/2
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Absolute Maximum Ratings(1)
Symbol
VIN VIN VCC TSTG TOPR IOUT
F29C51002T/F29C51002B
Parameter
Input Voltage (input or I/O pins) Input Voltage (A9 pin, OE) Power Supply Voltage Storage Temerpature (Plastic) Operating Temperature Short Circuit Current(2)
Commercial
-2 to +7 -2 to +13 -0.5 to +5.5 -65 to +125 0 to +70 200 (Max.)
Industrial
-2 to +7 -2 to +13 -0.5 to +5.5 -65 to +150 -40 to + 85 200 (Max.)
Unit
V V V C C mA
NOTE: 1. Stress greater than those listed unders "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Parameter Name
VIL VIH IIL IOL VOL VOH ICC1
Parameter
Input LOW Voltage Input HIGH Voltage Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Read Current
Test Conditions
VCC = VCC Min. VCC = VCC Max. VIN = GND to VCC, VCC = VCC Max. VOUT = GND to VCC, VCC = VCC Max. VCC = VCC Min., IOL = 2.1mA VCC = VCC Min, IOH = -400mA CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. CE = WE = VIL, OE = VIH, VCC = VCC Max. CE = OE = WE = VIH, VCC = VCC Max. CE = OE = WE = VCC - 0.3V, VCC = VCC Max. CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH, A9 = VH Max.
Min.
-- 2 -- -- -- 2.4 --
Max.
0.8 -- 1 10 0.4 -- 40
Unit
V V mA mA V V mA
ICC2 ISB ISB1 VH IH
Write Current TTL Standby Current CMOS Standby Current Device ID Voltage for A9 Device ID Current for A9
-- -- -- 11.5 --
50 2 100 12.5 50
mA mA mA V mA
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
AC Electrical Characteristics
(over all temperature ranges) Read Cycle
Parameter Name
tRC tAA tACS tOE tCLZ tOLZ tDF tOH
F29C51002T/F29C51002B
-70 Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time CE Low to Output Active OE Low to Output Active OE or CE High to Output in High Z Output Hold from Address Change
-90 Min.
90 -- -- -- 0 0 0 0
-12 Min.
120 -- -- -- 0 0 0 0
-15 Min.
150 -- -- -- 0 0 0 0
Min.
70 -- -- -- 0 0 0 0
Max.
-- 70 70 35 -- -- 30 --
Max.
-- 90 90 45 -- -- 40 --
Max.
-- 120 120 60 -- -- 50 --
Max.
-- 150 150 75 -- -- 60 --
Unit
ns ns ns ns ns ns ns ns
Program (Erase/Program) Cycle
Parameter Name Parameter
tWC tAS tAH tCS tCH tOES tOEH tWP tWPH tDS tDH tWHWH1 tWHWH2 tWHWH3 Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time OE Setup Time OE High Hold Time WE Pulse Width WE Pulse Width High Data Setup Time Data Hold Time Programming Cycle Sector Erase Cycle Chip Erase Cycle
-70
-90
-12
-15
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
70 0 45 0 0 0 0 35 20 30 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 10 3.0 90 0 45 0 0 0 0 45 30 30 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 10 120 0 50 0 0 0 0 50 35 30 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 10 3.0 150 0 50 0 0 0 0 50 35 30 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 10 3.0 ns ns ns ns ns ns ns ns ns ns ns ms ms sec
-- 3.0
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Waveforms of Read Cycle
tRC ADDRESS tAA CE tCE tOE OE tOLZ WE tCLZ I/O HIGH-Z tOH VALID DATA OUT tAA
F29C51002T/F29C51002B
tDF
VALID DATA OUT
HIGH-Z
51002-09
Waveforms of WE Controlled-Program Cycle
3rd bus cycle tWC tAS ADDRESS 5555H tCH CE PA tAH PA(2) tRC
OE tOES WE tCS tWPH tDS tDH I/O A0H PD(3) I/O7(1) DOUT tOH
51002-10
tWP
tWHWH1
tDF tOE
NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed.
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Waveforms of CE Controlled-Program Cycle
tWC ADDRESS 5555H PA tAS tAH WE PA(1)
F29C51002T/F29C51002B
tRC
OE tWP CE tOES tWPH tDS tDH I/O A0H PD(2) I/O7 DOUT tOH
51002-11
tWHWH1
tDF tOE
Waveforms of Erase Cycle(1)
tWC ADDRESS 5555H tAS 2AAAH 5555H tAH CE 5555H 2AAAH (5555H for Chip Erase) SA
OE tWP WE tCS tDS tDH I/O AAH 55H 80H AAH 55H tWPH tWHWH 2
3
(10H for Chip Erase) 30H
51002-12
NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase.
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Waveforms of DATA Polling Cycle
tCH CE tOE OE tOEH WE tCE tWHWH1 (2 or 3) I/O7 I/O7 I/O7
F29C51002T/F29C51002B
tDF
tOH HIGH-Z
VALID DATA OUT
I/O0-I/O6
I/O0-I/O6
INVALID
VALID DATA OUT
HIGH-Z
51002-13
Waveforms of Toggle Bit Cycle
CE tOEH WE
OE
I/O6 stop toggling tWHWH1 (2 or 3)
51002-14
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Functional Description
The F29C51002T/F29C51002B consists of 512 equally-sized sectors of 512 bytes each. The 16 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The F29C51002 is available in two versions: the F29C51002T with the Boot Block address starting from 3C000H to 3FFFFH, and the F29C51002B with the Boot Block address starting from 00000H to 3FFFFH.
F29C51002T 16KB Boot Block
F29C51002T/F29C51002B
F29C51002B 3FFFFH 3C000H
03FFFH 00000H 00000H 16KB Boot Block
51002-15
Read Cycle
A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1).
16KB Boot Block = 32 Sectors
Output Disable
Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state.
During the byte write cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled.
Sector Erase Cycle
The F29C51002T/F29C51002B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see Table 2). A sector must be first erased before it can be rewritten. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit status. The F29C51002T/F29C51002B is shipped fully erased (all bits = 1).
Standby
The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state.
Byte Write Cycle
The F29C51002T/F29C51002B is programmed on a byte-by-byte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2).
Table 1. Operation Modes Decoding
Decoding Mode
Read Byte Write Standby Autoselect Device ID Autoselect Manufacture ID Enabling Boot Block Protection Lock Disabling Boot Block Protection Lock Output Disable
CE
VIL VIL VIH VIL VIL VIL VH VIL
OE
VIL VIH X VIL VIL VH VH VIH
WE
VIH VIL X VIH VIH VIL VIL VIH
A0
A0 A0 X VIH VIL X X X
A1
A1 A1 X VIL VIL X X X
A9
A9 A9 X VH VH VH VH X
I/O
READ PD HIGH-Z CODE CODE X X HIGH-Z
NOTES: 1. X = Don't Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed.
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Table 2. Command Codes
First Bus Program Cycle Command Sequence Read Read Autoselect Mode Byte Program Chip Erase Address XXXXH 5555H 5555H Data F0H AAH AAH 2AAAH 2AAAH 55H 55H 5555H 5555H F0H 90H RA(1) RD(2) Second Bus Program Cycle Address Data Third Bus Program Cycle Address Data Fourth Bus Program Cycle Address Data
F29C51002T/F29C51002B
Fifth Bus Program Cycle Address Data
Six Bus Program Cycle Address Data
See table 3 for detail.
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD(4)
5555H
AAH AAH
2AAAH 2AAAH
55H 55H
5555H 5555H
80H 80H
5555H 5555H
AAH AAH
2AAAH 2AAAH
55H 55H
5555H SA(5)
10H 30H
Sector Erase 5555H
NOTES: 1. RA: Read Address 2. RD: Read Data 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. 5. SA(5): Sector Address
Chip Erase Cycle
The F29C51002T/F29C51002B features a chiperase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2). The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is "1".
Toggle Bit (I/O6)
The F29C51002T/F29C51002B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle.
Boot Block Protection Enabling/Disabling
The F29C51002T/F29C51002B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin LOW. The sector protection is disabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1.
Program Cycle Status Detection
There are two methods for determining the state of the F29C51002T/F29C51002B during a program (erase/write) cycle: DATA Polling (I/O7) and Toggle Bit (I/O6).
DATA Polling (I/O7)
The F29C51002T/F29C51002B features DATA polling to indicate the end of a program cycle. When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O7. Once the program cycle is completed, I/O7 will show true data, and the device is then ready for the next cycle.
Autoselect Mode
The F29C51002T/F29C51002B features an Autoselect mode to identify boot block locking status, device ID and manufacturer ID. Entering Autoselect mode is accomplished by applying a high voltage (VH) to the A9 Pin, or through a sequence of commands (as shown in table 2). Device will exit this mode once high voltage on A9 is removed or another command is loaded into the device.
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Boot Block Protection Status
In Autoselect mode, performing a read at address location 3CXX2H (F29C51002T) or 0CXX2H (F29C51002B) will indicate boot block protection status. If the data is 01H, the boot block is protected. If the data is 00H, the boot block is unprotected. This is also shown is table 3.
F29C51002T/F29C51002B
Manufacturer ID
In Autoselect mode, performing a read at address XXXX0H will determine the manufacturer ID. 40H is the manufacturer code for SyncMOS Flash.
Hardware Data Protection
VCC Detection: the program operation is inhibited when VCC is less than 3.5V. Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle. Program Inhibit: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle.
Device ID
In Autoselect mode, performing a read at address XXX1H will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 02H, the device is a Top Boot Block. If the data is A2H, the device is a Bottom Boot Block device (see Table 3).
Table 3. Autoselect Decoding
Address Decoding Mode
Boot Block Protection
Boot Block
Top Bottom
A0
VIL VIL VIH
A1
VIH VIH VIL
A2-A13
X X X
A14-A17
VIH VIL X
Data I/O0-I/O7
01H: protected 00H: unprotected 02H A2H
Device ID
Top Bottom
Manufacture ID NOTE: 1. X = Don't Care, VIH = HIGH, VIL = LOW.
VIL
VIL
X
X
40H
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Byte Program Algorithm
Write Byte-Write Command Sequence
F29C51002T/F29C51002B
Chip/Sector Erase Algorithm
Write Erase Command Sequence
Add/Data 5555H/AAH
Add/Data 5555H/AAH
2AAAH/55H Four Bus Cycle Sequence 5555H/A0H
2AAAH/55H
5555H/80H Six Bus Cycle Sequence
PA/PD
5555H/AAH
Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout
2AAAH/55H
Writing Completed
5555H/10H (Chip Erase) SA/30H (Sector Erase)
Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout
Erase Completed
51002-16
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
DATA Polling Algorithm
Read I/O7 Address = PBA(1)
F29C51002T/F29C51002B
Toggle Bit Algorithm
Read I/O6
No
I/O7 = Data
Read I/O6
Yes Yes Program Done No I/O6 Toggle
Program Done
51002-17
NOTE: 1. PBA: The byte address to be programmed.
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
Package Diagrams
32-pin Plastic DIP
1.660 MAX.
F29C51002T/F29C51002B
15 MAX
INDEX-1 EJECTOR MARK 0.545/0.555 INDEX-2 .600 TYP
+.004 .010 - .0004
.050 MAX
0.210 MAX 0.120 MIN .100 TYP +.012 .047 - 0 +.006 .018 - .002 0.010 MIN .032 +.012 -0
32-pin PLCC
20 19 18 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 17 16 15 14 13 12 11 10 9 8 7 6 5 .550 .003 .590 .005
.045X45 .450 .003 .490 .005 .050 TYP .110 .136 .003 .046 .003 .025 30
.017
3 - 6
.420 .003
3 - 6
3 - 6
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS
32-pin TSOP-I
Units in inches
0.787 0.008
F29C51002T/F29C51002B
Detail "A"
0.010 0.315 TYP. (0.319 MAX.)
0.024 0.004 0.724 TYP. (0.728 MAX.) SEATING PLANE See Detail "A" 0.005 MIN. 0.007 MAX. 0.032 TYP. 0.020 MAX. 0.020 SBC 0.003 MAX 0.009 0.002 0.035 0.002 0.047 MAX.
F29C51002T/F29C51002B V1.0 February 1998
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SyncMOS Technology Inc.
Sales Office :
4th Floor, No. 1, Creation Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan 30077 Tel : 886-3-5792988 Fax : 886-3-5792960
Note : 1. Publication date : November 1998 Rev. A 2. All data and specification are subject changed with Program (Erase/Program) Cycle as below description : a. Chip erase time : 2.0 sec 3.0 sec maximum. b. Byte program time : 20 usec 35 usec maximum
16
F29C51002T/F29C51002B V1.0 February 1998

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